SAM4L Datasheet, PDF (198/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
The oscillator is disabled by default after reset. When the oscillator is disabled, the XIN and
XOUT pins can be used as general purpose I/Os. When the oscillator is enabled, the XIN and
XOUT pins are controlled directly by the SCIF, overriding GPIO settings. When the oscillator is
configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin
can be used as general purpose I/O.
The oscillator is enabled by writing a one to the Oscillator Enable bit in the Oscillator Control reg-
ister (OSCCTRLn.OSCEN). Operation mode (external clock or crystal) is selected by writing to
the Oscillator Mode bit in OSCCTRLn (OSCCTRLn.MODE). The oscillator is automatically dis-
abled in certain sleep modes to reduce power consumption, as described in the Power Manager
chapter.
After a hard reset, or when waking up from a sleep mode where the oscillators were disabled,
the oscillator will need a certain amount of time to stabilize on the correct frequency. This start-
up time can be set in the OSCCTRLn register.
The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks
propagate to the digital logic.
The OSCn Ready bit in the Power and Clock Status Register (PCLKSR.OSCnRDY) is set when
the oscillator is stable and ready to be used as clock source. An interrupt can be generated on a
zero-to-one transition on OSCnRDY if the OSCnRDY bit in the Interrupt Mask Register
(IMR.OSCnRDY) is set. This bit is set by writing a one to the corresponding bit in the Interrupt
Enable Register (IER.OSCnRDY).
13.6.2
PLL Operation
Rev: 1.1.2.0
The device contains one Phase Locked Loop (PLL), which is controlled by the Phase Locked
Loop Interface (PLLIF). The PLL is disabled by default, but can be enabled to provide high fre-
quency source clocks for synchronous or generic clocks. The PLL can use different clock
sources as reference clock, refer to the “PLL Clock Sources” table in the SCIF Module Configu-
ration section for details. The PLL output is divided by a multiplication factor, and the PLL
compares the phase of the resulting clock to the reference clock. The PLL will adjust its output
frequency until the two compared clocks phases are equal, thus locking the output frequency to
a multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent the connected digital logic
from receiving a too high frequency and thus become unstable.
The PLL can be configured by writing the PLL Control Register (PLLn). To prevent unexpected
writes due to software bugs, write access to the PLLn register is protected by a locking mecha-
nism, for details refer to Section 13.7.7 ”Unlock Register” on page 222.
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