SAM4L Datasheet, PDF (542/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
23.7
User Interface
The GPIO controller manages all the GPIO pins. The pins are managed as 32-bit ports that are
configurable through a Peripheral Bus (PB) interface. Each port has a set of configuration regis-
ters. The overall memory map of the GPIO is shown below. The number of pins and hence the
number of ports is product specific.
Figure 23-6. Port Configuration Registers
Port 0 Configuration Registers
0x0000
Port 1 Configuration Registers
0x0200
Port 2 Configuration Registers
0x0400
Port n Configuration Registers
n*0x200
In the peripheral muxing table in the Package and Pinout chapter each GPIO pin has a unique
number. Note that the PA, PB, PC, and PX ports do not necessarily directly correspond to the
GPIO ports. To find the corresponding port and pin the following formulas can be used:
GPIO port = floor((GPIO number) / 32), example: floor((36)/32) = 1
GPIO pin = GPIO number % 32, example: 36 % 32 = 4
Table 23-2 shows the configuration registers for one port. Addresses shown are relative to the
port address offset. The specific address of a configuration register is found by adding the regis-
ter offset and the port offset to the GPIO start address. One bit in each of the configuration
registers corresponds to a GPIO pin.
23.7.1
Access Types
Most configuration register can be accessed in four different ways. The first address location can
be used to write the register directly. This address can also be used to read the register value.
The following addresses facilitate three different types of write access to the register. Performing
a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by the
operation. Performing a “clear” access, all bits written to one will be cleared. Bits written to zero
will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits writ-
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