SAM4L Datasheet, PDF (648/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
25.4 I/O Lines Description
Table 25-1. I/O Lines Description
Pin Name
RXD
Pin Description
Receive Serial Data
Type
Input
25.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
25.5.1 I/O Lines
The PICOUART pin is directly connected to the RXD pin, meaning the user doesn’t need to con-
figure the I/O Controller to give control of the pin to the PICOUART.
25.5.2
Power Management
PICOUART remains active when the system enters a Power Save Mode that disables its
CLK_PICOUART clock.
25.5.3 Clocks
The configuration clock for PICOUART (CLK_PICOUART) is generated by the Power Manager.
It can be enabled or disabled either manually through the user interface of the Power Manager
or automatically when the system enters a Power Save Mode that disables the clocks to the
peripheral bus modules. The running clock for PICOUART (CLK32) is generated by the Backup
Power Manager and is necessary for the PICOUART to operate. The source of this clock can be
either the RC32K or the OSC32K, which must be enabled using the Backup System Control
Interface.
25.5.4
Backup Power Management
The PICOUART wake-up line is connected to the Backup Power Manager. It allows to wake-up
the device from the current Power Save Mode. The user must first configure the Backup Power
Manager to enable the wake-up source accordingly.
25.5.5
Peripheral Events
The PICOUART peripheral events are connected via the Peripheral Event System. Refer to the
Peripheral Event System chapter for details.
25.6 Functional Description
25.6.1
Reception Operation
PICOUART Reception is enabled by writing a one to the RX Enable bit in the Control Register
(CR.RXEN). PICOUART Reception is disabled by writing a one to the RX Disable bit in the Con-
trol Register (CR.RXDIS). Reception is made by sampling the RXD pin on the CLK32 reference
clock. The decoding of the frame format is hardly coded and limited to the following
configuration:
• 9600 bauds if CLK32 is equal to 32,768 kHz
• One start bit
• Eight-bit data with LSB first
42023C–SAM–02/2013
648