SAM4L Datasheet, PDF (205/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
The generic clock CLK_DFLLx_SSG must be configured and enabled before SSG is enabled,
refer to Generic Clocks section for details. This clock sets the rate at which the SSG changes
the frequency of the DFLL clock to generate a spread spectrum. The frequency of this clock
should be higher than f_{CLK_DFLLx_REF} to ensure that the DFLLx can lock.
Optionally, the clock ticks can be qualified by a Pseudo Random Binary Sequence (PRBS) if the
PRBS bit in DFLLxSSG is one (DFLLxSSG.PRBS). This reduces the modulation effect of
CLK_DFLLx_SSG frequency onto f_{CLK_DFLLx}.
The step size of the SSG is selected by writing to the SSG Step Size field in DFLLxSSG (DFLLx-
SSG.STEPSIZE). If the step size is n, the output value from the SSG will be
incremented/decremented by n on every tick of the source clock. DFLLxSSG.STEPSIZE equal
to zero or one will result in a step size equal to one.
The amplitude of the frequency variation can be selected by writing an appropriate value to the
SSG Amplitude field in DFLLxSSG (DFLLxSSG.AMPLITUDE). If DFLLxSSG.AMPLITUDE is
larger than one, the sequence added to the FINE value will depend on both DFLLxSSG.AMPLI-
TUDE and DFLLxSSG.STEPSIZE, as shown in Figure 13-6. If DFLLxSSG.AMPLITUDE is zero
the SSG will toggle on the LSB of the FINE value. If DFLLxSSG.AMPLITUDE is one the SSG
will add the sequence {1,-1, 0} to FINE.
Figure 13-6. Spread Spectrum Sequence added to FINE Value
A M P L IT U D E
S T E P S IZ E
t
13.6.3.8
The Spread Spectrum Generator is available in both open and closed loop mode.
When spread spectrum is enabled in closed loop mode, and the DFLLxSSG.AMPLITUDE value
is high, an overflow/underflow in FINE is more likely to occur.
Wake From Power Save Modes
DFLLx may optionally reset its lock bits when waking from a Power Save Mode which disables
the DFLLx. This is configured by the Lose Lock After Wake bit in DFLLxCONF (DFLLx-
CONF.LLAW). If DFLLxCONF.LLAW is zero the DFLL will be re-enabled and start running with
the same configuration as before going to sleep even if the reference clock is not available. The
locks will not be lost. When the reference clock has restarted, the FINE tracking will quickly com-
pensate for any frequency drift during sleep if DFLLxCONF.STABLE is zero. If
42023C–SAM–02/2013
205