SAM4L Datasheet, PDF (993/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
38.6.5
Note that the ADC works differentially in single-ended mode as well, as long as the positive input
has a higher voltage than the negative.
ADC Clock Configuration
The ADCIFE generates an internal clock named CLK_ADC that is used by the Analog-to-Digital
Converter cell to perform conversions. The CLK_ADC is selected by writing to the CLKSEL bit in
the Configuration Register (CFG). The CLK_ADC frequency is the frequency of the clock
selected by the CLKSEL bit divided by the prescaler field in the Configuration
Register(CFG.PRESCAL).
The value of th frequency must be defined in order to provide an ADC clock frequency according
to the maximum sampling rate parameter given in the Electrical Characteristics section. Failing
to do so may result in incorrect Analog-to-Digital Converter operation.
The ADC cell converts an input voltage in 6 CLK_ADC periods and takes at least SHTIM+1
GCLK periods to sample for a 12-bit resolution.
Thus, the maximum achievable ADC sampling frequency is:
F_-----(_--C_----L_----K_----A_----D_-----C_----)_-
6
If a 8-bit result is generated, the maximum ADC sampling frequency is
F_-----(_--C_----L_----K_----A_----D_-----C_-----)
4
38.6.6
Power Reduction Mode
The Power Reduction Mode maximizes power saving by automatically deactivating the Analog-
to-Digital Converter cell when it is not being used for conversions. The Power Reduction Mode is
enabled by writing a one to the Disable ADC(DIS) bit in the Control register (CR.DIS).
Before entering power reduction mode the user must make sure the ADCIFE is idle and that the
Analog-to-Digital Converter cell is inactive. To make sure the ADCIFE is idle, write a zero to the
Trigger Selection (TRGSEL) field in the Sequencer Configuration Register (SEQCFG) and wait
for the sequencer busy (SBUSY) bit in the Status Register (SR) to be cleared. Note that by
deactivating the Analog-to-Digital Converter cell, a startup time penalty as defined in the
STARTUP field in the timing register (TIM) will apply on the next conversion.
The ADCIFE has the possibility to adjust the power consumption of the ADC cell according to
the frequency range used. The SPEED field in the CFG register must be written to the right
value.
38.6.7
Power-up and Startup Time
The Analog-to-Digital Converter cell has a startup time when the cell is activated for the first
time. This startup time is at least 12 ADC_CLK. This timing should be manage by the user by
setting the startup time field in the Timing Configuration register (TIM.STARTUP). The enable
startup bit in the Timing Configuration register (TIM.ENSTUP) allows to enable or not the startup
time.
For power-up and startup time values of the ADC cell, refer to the ADC cell chapter.
38.6.8
Operation Start/Stop
To reset ADCIFE to its initial state, user can enable the ADCIFE after it was previously disabled
thanks to the Enable bit in the Control register (CR.EN) and the Disable bit in the Control register
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