SAM4L Datasheet, PDF (210/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

Figure 13-9. Fractional Prescaler Generation
ATSAM4L4/L2
Divider
Mask
FPCLK
CKSEL
FPMUL FPDIV
FPEN
The FP is enabled by writing a one to the FPEN bit in the Fractional Prescaler Control Register
(FPCR).
The user can select a clock source for the FP by writing to the CKSEL field of the FPCR register.
The user must configure the FP frequency by writing to the FPMUL and FPDIV fields of the
FPMUL and FPDIV registers. FPMUL and FPDIV must not be equal to zero and FPDIV must be
greater or equal to FPMUL. This results in the output frequency:
f_FPCLK = f_SRC * FPMUL/ (2*FPDIV)
The CKSEL field can not be changed dynamically but the FPMUL and FPDIV fields can be
changed on-the-fly.
• Jitter description
As described in Figure 13-10, the CLKFP half period lengths are integer multiples of the source
clock period but are not always equals. However the difference between the low level half period
length and the high level half period length is at the most one source clock period.
This induces when FPDIV is not an integer multiple of FPMUL a jitter on the FPCLK. The more
the FPCLK frequency is low, the more the jitter incidence is reduced.
Figure 13-10. Fractional Prescaler Jitter Examples
SRC clock
FMUL= 5
FDIV=5
FPCLK _FMUL=3
FDIV=10
FMUL=7
FDIV=9
13.6.8
Generic Clocks
Rev: 1.1.2.0
42023C–SAM–02/2013
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