SAM4L Datasheet, PDF (451/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
(EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD)
register.
19.5.5
AST wakeup
The AST can wake up the system by trigerring a PM interrupt. A wakeup can be generated when
the counter overflows, when the counter reaches the selected alarm value, or when the selected
prescaler bit has a 0-to-1 transition. This wakeup is propagated to the PM and a PM interrupt is
generated if enabled.
The AST wakeup is enabled by writing a one to the corresponding bit in the Wake Enable Regis-
ter (WER). When the CPU wakes from sleep, the wake signal must be cleared by writing a one
to the corresponding bit in SCR to clear the internal wake signal to the sleep controller. If the
wake signal is not cleared after waking from sleep, the next sleep instruction will have no effect
because the CPU will wake immediately after this sleep instruction.
The AST wakeup can wake the CPU from any sleep mode where the source clock is active. The
AST wakeup can be configured independently of the interrupt masking.
19.5.6
Backup Mode
If the AST is configured to use a clock that is available in Backup mode, the AST can be used to
wake up the system from backup. Both the alarm wakeup, periodic wakeup, and overflow
wakeup mechanisms can be used in this mode.
When waking up from Backup mode all control registers will have the same value as before the
backup was entered, except the Interrupt Mask Register (IMR). IMR will be reset with all inter-
rupts turned off. The software must first reconfigure the NVIC and then enable the interrupts in
the AST to again receive interrupts from the AST.
The CV register will be updated with the current counter value directly after wakeup from shut-
down. The SR will show the status of the AST, including the status bits set during backup
operation.
When waking up the system from backup the CPU will start executing code from the reset start
address.
19.5.7
Digital Tuner
The digital tuner adds the possibility to compensate for a too-slow or a too-fast input clock. The
ADD bit in the Digital Tuner Register (DTR.ADD) selects if the prescaler frequency should be
reduced or increased. If ADD is ‘0’, the prescaler frequency is reduced:
⎛
⎞
f_TUNED=
⎜
f_{0 ⎜⎜} 1
⎝
–
---------------------------------------¹----------------------------------------⎟⎟
roundup
⎛
⎝
V^-----A^-2---L^5---6U^-----E^{--⎠⎞}
⋅
(2^EXP)
+
1_⎠⎟
where f_TUNED is the tuned frequency, f₀ is the original prescaler frequency, and VALUE and EXP
are the corresponding fields to be programmed in DTR. Note that DTR.EXP must be greater
than zero. Frequency tuning is disabled by programming DTR.VALUE as zero.
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