SAM4L Datasheet, PDF (107/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Depending on the reset source, when a Reset occurs, some parts of the device are not always
reset. Only the Power On Reset (POR) will force a whole device reset. Refer to the table in the
Module Configuration section at the end of this chapter for further details. The latest reset cause
can be read in the RCAUSE register, and can be read during the applications boot sequence in
order to determine proper action.
The table below lists parts of the device that are reset, depending on the reset type. The cause
of the last reset can be read from the RCAUSE register. This register contains one bit for each
reset source, and can be read during the boot sequence of an application.
10.6.6
Clock Failure Detector
This mechanism allows switching the main clock to the safe RCSYS clock, when the main clock
source is considered off. This may happen when a external crystal is selected as the clock
source of the main clock but the crystal is not mounted on the board. The mechanism is to
detect, during a RCSYS period, at least one rising edge of the main clock. If no rising edge is
seen the clock is considered failed.
Example:
* RCSYS = 115khz
=> Failure detected if the main clock is < 115 kHz
As soon as the detector is enabled, the clock failure detector will monitor the divided main clock.
Note that the detector does not monitor if the RCSYS is the source of the main clock, or if the
main clock is temporarily not available (startup-time after a wake-up, switching timing etc.), or in
SLEEP mode where the main clock is driven by the RCSYS (SLEEP mode level 3). When a
clock failure is detected, the main clock automatically switches to the RCSYS clock and the CFD
interrupt is generated if enabled.
The MCCTRL register that selects the source clock of the main clock is changed by hardware to
indicate that the main clock comes from RCSYS.
10.6.7 Interrupts
The PM has a number of interrupts:
• AE - Access Error,
– A lock protected register is written to without first being unlocked.
• CKRDY - Clock Ready:
– New Clock Select settings in the CPUSEL/PBxSEL registers have taken effect. (A
zero-to-one transition on SR.CKRDY is detected).
• CFD - Clock Failure Detected:
– The system detects that the main clock is not running.
• WAKE - Asynchronous wake Detected:
– An asynchronous wakeup from a peripheral is detetcted.
The Interrupt Status Register contains one bit for each interrupt source. A bit in this register is
set on a zero-to-one transition of the corresponding bit in the Status Register (SR), and cleared
by writing a one to the corresponding bit in the Interrupt Clear Register (ICR). The interrupt
sources will generate an interrupt request if the corresponding bit in the Interrupt Mask Register
is set. The interrupt sources are ORed together to form one interrupt request. The Power Man-
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