SAM4L Datasheet, PDF (608/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 24-46. Start Frame Delimiter
Preamble Length
is set to 0
Manchester
encoded
data ^Txd
SFD
Manchester
encoded
data
Txd
SFD
Manchester
encoded
data ^Txd
SFD
DATA
One bit start frame delimiter
DATA
Command Sync
start frame delimiter
DATA
Data Sync
start frame delimiter
Manchester Drift Compensation
The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery
system that allows for sub-optimal clock drifts without further user intervention. Drift compensa-
tion is only available in 16x oversampling mode (MR.OVER is zero). If the RXD event is one 16th
clock cycle from the expected edge, it is considered as normal jitter and no corrective action will
be taken. If the event is two to four 16th’s early, the current period will be shortened by a 16th. If
the event is two to three 16th’s after the expected edge, the current period will be prolonged by a
16th.
Figure 24-47. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling
point
24.6.16.2
Synchro.
Error
Synchro.
Jump
Expected edge
Tolerance
Sync
Jump
Synchro.
Error
Manchester Decoder
The Manchester decoder can detect selectable preamble sequences and start frame delimiters.
The Receiver Manchester Polarity bit in the “Manchester Configuration Register”
(MAN.RX_MPOL) selects input stream polarity. The Receiver Preamble Length field
(MAN.RX_PL) specifies the length characteristics of detectable preambles. If MAN.RX_PL is
zero, the preamble pattern detection will be disabled. The Receiver Preamble Pattern field
(MAN.RX_PP) selects the pattern to be detected. See Figure 24-45 for available preamble pat-
terns. Figure 24-48 illustrates two types of Manchester preamble pattern mismatches.
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