SAM4L Datasheet, PDF (741/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
28.7.3 Clocks
The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. It is rec-
ommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an
undefined state.
28.7.4 DMA
The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIS.
28.7.5 Interrupts
The TWIS interrupt request lines are connected to the NVIC. Using the TWIS interrupts requires
the NVIC to be programmed first.
28.7.6
Debug Operation
When an external debugger forces the CPU into debug mode, the TWIS continues normal oper-
ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
28.8 Functional Description
28.8.1
Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
28-4 on page 741).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
28-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 28-3. START and STOP Conditions
TWD
TWCK
Start
Stop
Figure 28-4. Transfer Format
TWD
TWCK
Start Address R/W Ack
Data
Ack
Data
Ack Stop
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