SAM4L Datasheet, PDF (785/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
29.8.3 Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x08
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
TXURCH
-
-
-
-
15
14
13
12
11
10
-
-
-
-
-
-
9
8
RXORCH
7
6
5
4
3
2
1
0
-
TXUR
TXRDY
TXEN
-
RXOR
RXRDY
RXEN
• TXURCH: Transmit Underrun Channel
This field is cleared when SCR.TXUR is written to one.
Bit i of this field is set when a transmit underrun error occurred in channel i (i=0 for first channel of the frame).
• RXORCH: Receive Overrun Channel
This field is cleared when SCR.RXOR is written to one.
Bit i of this field is set when a receive overrun error occurred in channel i (i=0 for first channel of the frame).
• TXUR: Transmit Underrun
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an underrun error occurs on the THR register or when the corresponding bit in SSR is written to one.
• TXRDY: Transmit Ready
This bit is cleared when data is written to THR.
This bit is set when the THR register is empty and can be written with new data to be transmitted.
• TXEN: Transmitter Enabled
This bit is cleared when the Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request.
This bit is set when the Transmitter is effectively enabled, following a CR.TXEN request.
• RXOR: Receive Overrun
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an overrun error occurs on the RHR register or when the corresponding bit in SSR is written to one.
• RXRDY: Receive Ready
This bit is cleared when the RHR register is read.
This bit is set when received data is present in the RHR register.
• RXEN: Receiver Enabled
This bit is cleared when the Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request.
This bit is set when the Receiver is effectively enabled, following a CR.RXEN request.
42023C–SAM–02/2013
785