HD64F38602R Datasheet, PDF (95/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
The clock pulse generator is provided on-chip, including both a system clock pulse generator and
a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator,
system clock divider, and on-chip oscillator. The subclock pulse generator consists of a subclock
oscillator, on-chip oscillator clock divider, and subclock divider. Figure 4.1 shows a block
diagram of the clock pulse generators.
E7_2
OSC1
OSC2
System
clock
oscillator
φOSC
(fOSC)
On-chip ^Rosc
oscillator _(fROSC)
System clock pulse
generator
X1
Subclock _φW
X2
oscillator _(fW)
On-chip
oscillator ^Rosc/32
clock divider
φOSC
(fOSC)
φW
(fW)
System
clock
divider
φOSC
φOSC/8
φOSC/16
φOSC/32
φOSC/64
φW/2
Subclock _φW/4
divider _φW/8
Subclock pulse generator
[Legend]
OSCCR: Oscillator control register
OSCCR
φ
Prescaler S
(13 bits)
Rosc
φ/2
to
φ/8192
φW
φSUB
Prescaler W
(8 bits)
φW/2
φW/4
φ_W/8
to
φ_W/1024
Figure 4.1 Block Diagram of Clock Pulse Generators
The reference clock signals that drive the CPU and on-chip peripheral modules are φ and φ_SUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2. φ_W/4, which is
1/4th of the watch clock φ_W, is divided by prescaler W to become a clock signal from φ_W/1024 to
φ_W/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
CPG0200A_000020020200
Rev. 3.00 May 15, 2007 Page 63 of 516
REJ09B0152-0300