HD64F38602R Datasheet, PDF (377/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
16.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 16.3 shows the contents of
each interrupt request.
Table 16.3 Interrupt Requests
Interrupt Request Abbreviation
Transmit Data Empty TXI
Transmit End
TEI
Receive Data Full
RXI
STOP Recognition STPI
NACK Receive
NAKI
Arbitration
Lost/Overrun
Interrupt Condition
(TDRE = 1) ^• (TIE = 1)
(TEND = 1) ^• (TEIE = 1)
(RDRF = 1) ^• (RIE = 1)
(STOP = 1) ^• (STIE = 1)
{(NACKF = 1) + (AL = 1)} ^•
(NAKIE = 1)
Clock
Synchronous
I²C Mode Mode
{
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×
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×
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When interrupt conditions described in table 16.3 are 1 and the I bit in CCR is 0, the CPU
executes interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
Rev. 3.00 May 15, 2007 Page 345 of 516
REJ09B0152-0300