HD64F38602R Datasheet, PDF (282/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2)
φ
4 MHz
8 MHz
Bit Rate (bit/s) n N Error (%) n N Error (%)
200
3 77 0.16
3 155 0.16
250
2 249 0.00
3 124 0.00
300
2 207 0.16
3 103 0.16
500
2 124 0.00
2 249 0.00
1k
2 62 −0.79
2 124 0.00
2.5k
2 24 0.00
2 49 0.00
5k
0 199 0.00
2 24 0.00
10k
0 99 0.00
0 199 0.00
25k
0 39 0.00
0 79 0.00
50k
0 19 0.00
0 39 0.00
100k
0 9 0.00
0 19 0.00
250k
0 3 0.00
0 7 0.00
500k
0 1 0.00
0 3 0.00
1M
0* 0* 0.00*
0 1 0.00
Note: * Continuous transmission/reception is not possible.
The value set in BRR is given by the following formula:
N=
φ
4 × 2²ⁿ × B
–1
10 MHz
n N Error (%)
3 194 0.16
3 155 0.16
3 129 0.16
3 77 0.16
2 155 0.16
2 62 −0.79
2 30 0.81
0 249 0.00
0 99 0.00
0 49 0.00
0 24 0.00
0 9 0.00
0 4 0.00

B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 14.7.)
Table 14.7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φ_W*
0
1
2
φ/16
1
0
3
φ/64
1
1
Note: * In subactive or subsleep mode, the SCI3 can be operated only when the CPU operating
clock is φ_W.
Rev. 3.00 May 15, 2007 Page 250 of 516
REJ09B0152-0300