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HD64F38602R Datasheet, PDF (281/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1)
φ
32.8 kHz
38.4 kHz
Bit Rate (bit/s) n N Error (%) n N Error (%)
200
0 40 0.00
0 47 0.00
250
0 32 −0.61
0 37 1.05
300
0 26 1.23
0 31 0.00
500
0 15 2.50
0 18 1.05
1k
0 7 2.50

2.5k


5k


10k


25k


50k


100k


250k


500k


1M


Note: * Continuous transmission/reception is not possible.
2 MHz
n N Error (%)
2 155 0.16
2 124 0.00
2 103 0.16
2 62 −0.79
2 30 0.81
0 199 0.00
0 99 0.00
0 49 0.00
0 19 0.00
0 9 0.00
0 4 0.00
0 1 0.00
0* 0* 0.00*

Rev. 3.00 May 15, 2007 Page 249 of 518
REJ09B0152-0300