HD64F38602R Datasheet, PDF (372/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
16.4.7 Noise Canceler
The logic levels on the SCL and SDA pins are internally latched via noise cancelers. Figure 16.16
shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or SDA
input signal
C
D
Q
Latch
C
D
Q
Latch
Match detector
Internal
SCL or SDA
signal
Sampling
clock
System clock
period
Figure 16.16 Block Diagram of Noise Conceler
16.4.8 Example of Use
Flowcharts in respective modes that use the I²C bus interface 2 are shown in figures 16.17 to
16.20.
Rev. 3.00 May 15, 2007 Page 340 of 516
REJ09B0152-0300