HD64F38602R Datasheet, PDF (275/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.8 Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF.
Tables 14.2 and 14.3 show the relationship between the N setting in BRR and the n setting in bits
CKS1 and CKS0 in SMR in asynchronous mode. Table 14.5 shows the maximum bit rate for each
frequency in asynchronous mode. The values shown in these tables are values in active (high-
speed) mode. When the ABCS bit in SEMR is set to 1 in asynchronous mode, the maximum bit
rate in table 14.5 is doubled. Table 14.6 shows the relationship between the N setting in BRR and
the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values shown in
table 14.6 are values in active (high-speed) mode. The N setting in BRR and error for other
operating frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode and ABCS Bit is 0]
N=
φ
32 × 2²ⁿ × B
–1
Error (%) = ^{B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 14.2)} × 100
R (bit rate in left-hand column in table 14.2)
[Asynchronous Mode and ABCS Bit is 1]
N=
φ
16 × 2²ⁿ × B
–1
Error (%) = ^{B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 14.3)} × 100
R (bit rate in left-hand column in table 14.3)
[Legend]
B: Bit rate (bit/s)
N:
BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ:
Operating frequency (Hz)
n:
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 14.4)
Rev. 3.00 May 15, 2007 Page 243 of 518
REJ09B0152-0300