HD64F38602R Datasheet, PDF (321/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.3.3 SS Mode Register (SSMR)
SSMR is a register that selects MSB-first or LSB-first, clock polarity, clock phase, and transfer
clock rate.
Initial
Bit
Bit Name Value R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
Selects whether data transfer is performed in MSB-first
or LSB-first.
0: LSB-first
1: MSB-first
6
CPOS
0
R/W Clock Polarity Select
Selects the clock polarity of SSCK.
0: Idle state = high
1: Idle state = low
5
CPHS
0
R/W Clock Phase Select
Selects the clock phase of SSCK.
0: Data change at first edge
1: Data latch at first edge
4, 3 
All 0

Reserved
These bits are always read as 0.
2
CKS2
0
R/W Transfer clock rate select
1
CKS1
0
0
CKS0
0
R/W Sets transfer clock rate (prescaler division ratio) when
R/W ^{the internal clock is selected.}
The system clock (φ) is halted in subactive mode or
subsleep mode. Select φ /2 in these modes.
SUB
000: φ/256
001: φ/128
010: φ/64
011: φ/32
100: φ/16
101: φ/8
110: φ/4
111: φ /2
SUB
Rev. 3.00 May 15, 2007 Page 289 of 518
REJ09B0152-0300