HD64F38602R Datasheet, PDF (532/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
5.3.2 Direct Transition from Active 92
(High-Speed) Mode to Subactive
Mode
Added
When a SLEEP instruction is executed in active (high-
speed) mode while the SSBY, TMA3, and LSON bits in
SYSCR1 are set to 1 and the DTON bit in SYSCR2 is
set to 1, a transition is made to subactive mode via
watch mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (2).
Example: When φw/8 is selected as the subactive
operating clock after the transition
Direct transition time = (2 + 1) × 1tosc + 14 × 8tw =
3tosc + 112tw
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
5.3.3 Direct Transition from Active 92
(Medium-Speed) Mode to Active
(High-Speed) Mode
Added
When a SLEEP instruction is executed in active
(medium-speed) mode while the SSBY and LSON bits
in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is cleared to 0, and the DTON bit in SYSCR2 is set to
1, a transition is made to active (high-speed) mode via
sleep mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (3).
Example: When φosc/8 is selected as the CPU
operating clock before the transition
Direct transition time = (2 + 1) × 8tosc + 14 × 1tosc =
38tosc
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 500 of 516
REJ09B0152-0300