HD64F38602R Datasheet, PDF (383/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 17 A/D Converter
17.3.2 A/D Mode Register (AMR)
AMR sets the A/D conversion time, and selects the external trigger and analog input pins.
Initial
Bit Bit Name Value R/W Description
7

0

Reserved
This bit is always read as 0 and cannot be modified.
6
TRGE
0
R/W External Trigger Select
Enables or disables the A/D conversion start by the
external trigger input.
0: Disables the A/D conversion start by the external
trigger input.
1: Starts A/D conversion at the rising or falling edge of
the ADTRG pin
The edge of the ADTRG pin is selected by the
ADTRGNEG bit in IEGR.
5
CKS1
4
CKS0
0
R/W Clock Select
0
R/W Select the A/D conversion clock source.
00: φ/8
(conversion time = 124 states (max.)
(reference clock = φ)
01: φ/4
(conversion time = 62 states (max.)
(reference clock = φ)
10: φ/2
(conversion time = 31 states (max.)
(reference clock = φ)
11: φw/2
(conversion time = 31 states (max.)
(reference clock = φ )
SUB
While CKS1 and CKS0 are all 1 in subactive or
subsleep mode, the A/D converter can be used only
when the CPU operating clock is φw.
Rev. 3.00 May 15, 2007 Page 351 of 518
REJ09B0152-0300