HD64F38602R Datasheet, PDF (385/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 17 A/D Converter
17.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing
the conversion time or analog input channel, in order to prevent incorrect operation, first clear the
bit ADSF to 0 in ADSR.
17.4.1 A/D Conversion
1. A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D result register.
3. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2
is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF
bit is automatically cleared to 0 and the A/D converter enters the wait state.
17.4.2 External Trigger Input Timing
The A/D converter can also start A/D conversion by input of an external trigger signal. External
trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and the
TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit
in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D
conversion.
Figure 17.2 shows the timing.
Note: * The ADTRG input pin is shared with the TEST pin. Therefore when the pin is used as
the ADTRG pin, reset should be cleared while the 0-fixed signal is input to the TEST
pin. Then the ADTSTCHG bit should be set to 1 after the TEST signal is fixed.
φ
ADTRG
(when
ADTRGNEG = 0)
ADSF
A/D conversion
Figure 17.2 External Trigger Input Timing
Rev. 3.00 May 15, 2007 Page 353 of 518
REJ09B0152-0300