HD64F38602R Datasheet, PDF (539/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
Figure 14.4 Sample SCI3
Initialization Flowchart
Figure 14.6 Sample Serial
Transmission Flowchart
(Asynchronous Mode)
14.5 Operation in Clock
Synchronous Mode
14.6 Multiprocessor
Communication Function
Page Revisions (See Manual for Details)
258 Modified
Wait
260
1-bit interval elapsed?
Yes
Set SPC3 bit in SPCR to 1
Set TE and RE bits in
SCR to 1, and set RIE, TIE
and TEIE bits.
<Initialization completion>
Modified
No
[4]
[[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR to 1. Setting bits
TE and RE enables the TXD3 and RXD3
pins to be used. Also set the RIE, TIE,
and TEIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
264
270
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
Clear SPC3 bit in SPCR and
TE bit in SCR to 0*
<End>
[3] To output a break in serial transmission,
after setting PCR to 1 and PDR to 0,
clear the SPC3 bit in SPCR and the TE
bit in SCR to 0.
Note: * When the SPC3 bit in SPCR is cleared to 0,
the pin functions as an I/O port.
Deleted
… After 8-bit data is output, the transmission line holds
the MSB state. In clock synchronous mode, no parity or
multiprocessor bit is added.
This section is deleted.
Rev. 3.00 May 15, 2007 Page 507 of 516
REJ09B0152-0300