HD64F38602R Datasheet, PDF (333/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Dummy read on SSRDR
Yes
[2]
Last reception?
No
Read ORER
Yes
[3]
ORER = 1?
[4]
No
No
Read RDRF
RDRF = 1?
Yes
Read receive data
in SSRDR
[1] After setting each register in the SSU,
dummy read on SSRDR is performed
and reception is started.
[2] Determine whether the last one byte of
data is received. When the last one byte
of data is received, set to stop reception
after the data is received.
[3][6] When a receive error occurs, clear the
ORER flag to 0 after the ORER flag in
SSSR is read and an appropriate error
processing is performed. When the ORER
flag is set to 1, transmission/reception
cannot be started again.
[4] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
[5]
[6]
No
[7]
Set RSSTP to 1
Read ORER
ORER = 1?
No
Read RDRF
RDRF = 1?
Yes
RE = 0, RSSTP = 0
Read receive data
in SSRDR
[5] Before the last one byte of data is received,
set the RSSTP bit to 1 and reception is stopped
after the data is received.
Yes
[7] Confirm that the RDRF bit is 1. To end
reception, clear the RE and RSSTP bits to
0 and then read the last receive data. If the
Overrun error SSRDR bit is read before clearing the RE bit,
processing reception is started again.
End
Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)
Rev. 3.00 May 15, 2007 Page 301 of 518
REJ09B0152-0300