HD64F38602R Datasheet, PDF (93/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.8.5 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC.
When an interrupt request is generated, an interrupt is requested to the CPU. At that time, if the
CPU is executing an instruction that disables interrupts, the CPU always executes the next
instruction after the instruction execution is completed.
3.8.6 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is
not accepted until the transfer is completed.
With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during
transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is
issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the
stack in this case is the address of the next instruction.
Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W
R4,R4
BNE
L1
3.8.7 IENR Clearing
When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt
flag register is cleared, the interrupt request should be masked (I bit = 1). If the above operation is
executed while the I bit is 0 and conflict between the instruction execution and the interrupt
request generation occurs, exception handling, which corresponds to the interrupt request
generated after instruction execution of the above operation is completed, is executed.
Rev. 3.00 May 15, 2007 Page 61 of 516
REJ09B0152-0300