HD64F38602R Datasheet, PDF (192/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
10.3.4 Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit
7
6 to 4
3
2
Bit Name
OVF

IMFD
IMFC
Initial
Value
0
All 1
0
0
R/W
R/(W)*

R/(W)*
R/(W)*
Description
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
Reserved
These bits are always read as 1.
Input Capture/Compare Match Flag D
[Setting conditions]
• TCNT = GRD when GRD functions as an output
compare register
• The TCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
[Clearing condition]
Read IMFD when IMFD = 1, then write 0 in IMFD
Input Capture/Compare Match Flag C
[Setting conditions]
• TCNT = GRC when GRC functions as an output
compare register
• The TCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
[Clearing condition]
Read IMFC when IMFC = 1, then write 0 in IMFC
Rev. 3.00 May 15, 2007 Page 160 of 516
REJ09B0152-0300