HD64F38602R Datasheet, PDF (80/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.4.2 Interrupt Enable Register 1 (IENR1)
IENR1 enables the RTC, IRQAEC, IRQ1, and IRQ0 interrupts.
Initial
Bit
Bit Name Value R/W Description
7
IENRTC 0
R/W RTC Interrupt Request Enable
The RTC interrupt request is enabled when this bit is set
to 1.
6 to 3 
All 0

Reserved
The write value should always be 0.
2
IENEC2 0
R/W IRQAEC Interrupt Request Enable
The IRQAEC interrupt request is enabled when this bit is
set to 1.
1
IEN1
0
R/W IRQ1 Interrupt Request Enable
The IRQ1 interrupt request is enabled when this bit is set
to 1.
0
IEN0
0
R/W IRQ0 Interrupt Request Enable
The IRQ0 interrupt request is enabled when this bit is set
to 1.
Rev. 3.00 May 15, 2007 Page 48 of 516
REJ09B0152-0300