HD64F38602R Datasheet, PDF (537/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
Table 12.2 The Value of "xx"
Section 13 Asynchronous Event
Counter (AEC)
13.3.6 Event Counter H (ECH)
Page Revisions (See Manual for Details)
211 Added
222 Modified
Bit Bit Name Description
7 ECH7 _{Either the external asynchronous event AEVH pin,}
6 ECH6 φ/2, φ/4, or φ/8, or the overflow signal from lower 8-
5 ECH5 ^{bit counter ECL can be selected as the input clock}
source. ECH can be cleared to H'00 when the
4 ECH4
CRCH bit in ECCSR is cleared to 0.
3 ECH3
2 ECH2
1 ECH1
0 ECH0
13.3.7 Event Counter L (ECL) 222
Section 14 Serial Communication 231
Interface 3 (SCI3, IrDA)
14.3.5 Serial Mode Register
235
(SMR)
Modified
Bit Bit Name Description
7 ECL7
6 ECL6
5 ECL5
4 ECL4
Either the external asynchronous event AEVL pin,
φ/2, φ/4, or φ/8 can be selected as the input clock
source. ECL can be cleared to H'00 when the
CRCL bit in ECCSR is cleared to 0.
3 ECL3
2 ECL2
1 ECL1
0 ECL0
Deleted
The serial communication interface 3 (SCI3) can handle
both asynchronous and clock synchronous serial
communication. In the asynchronous method, serial
data communication can be carried out using standard
asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an
Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial
communication between processors (multiprocessor
communication function).
Modified
Bit Bit Name Description
2 MP
5-Bit CommunicationWhen this bit is set to 1, the
5-bit communication format is enabled. Make sure
to set bit 5 (PF) to 1 when setting this bit (MP) to 1.
Rev. 3.00 May 15, 2007 Page 505 of 516
REJ09B0152-0300