HD64F38602R Datasheet, PDF (323/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.3.5 SS Status Register (SSSR)
SSSR is a register that sets interrupt flags.
Initial
Bit
Bit Name Value R/W Description
7
—
0
—
Reserved
This bit is always read as 0.
6
ORER
0
R/(W)* Overrun Error Flag
Indicates that the RDRF bit is abnormally terminated in
reception because an overrun error has occurred.
SSRDR retains received data before the overrun error
occurs and the received data after the overrun error
occurs is lost. When this bit is set to 1, subsequent serial
reception cannot be continued. When the MSS bit in
SSCRH is 1, this is also applied to serial transmission.
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing condition]
• When 0 is written to this bit after reading 1
5, 4 
All 0

Reserved
These bits are always read as 0.
3
TEND
0
R/(W)* Transmit End
[Setting condition]
• When the last bit of data is transmitted, the TDRE bit
is 1
[Clearing conditions]
• When 0 is written to this bit after reading 1
• When data is written in SSTDR
Rev. 3.00 May 15, 2007 Page 291 of 518
REJ09B0152-0300