HD64F38602R Datasheet, PDF (346/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
16.3 Register Descriptions
The I²C bus interface 2 has the following registers.
• I²C bus control register 1 (ICCR1)
• I²C bus control register 2 (ICCR2)
• I²C bus mode register (ICMR)
• I²C bus interrupt enable register (ICIER)
• I²C bus status register (ICSR)
• Slave address register (SAR)
• I²C bus transmit data register (ICDRT)
• I²C bus receive data register (ICDRR)
• I²C bus shift register (ICDRS)
16.3.1
I²C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I²C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Initial
Bit Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to
the port/serial function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W Reception Disable
This bit enables or disables the next operation when
TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Rev. 3.00 May 15, 2007 Page 314 of 516
REJ09B0152-0300