HD64F38602R Datasheet, PDF (139/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 6.2 Boot Mode Operation
Host Operation
Processing Contents
Communication
Contents
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 ^{. . .} H'00
H'00
H'55
Section 6 ROM
LSI Operation
Processing Contents
Branches to boot program after releasing
reset state.
Boot program initiation
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end code.
H'55 reception.
Boot program
erase error
H'AA reception
H'FF
H'AA
Checks flash memory data, erases all flash
memory blocks when data has been written
to and then transmits data H'AA to host.
(If erasure fails, transmits data of H'FF to
host and aborts operation.)
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(lower byte following upper byte)
Transmits 1-byte of programming
control program (repeated for N times)
Low-order byte
and high-order byte
Echoback
Echobacks the 2-byte data
received to host.
H'XX
Echoback
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Rev. 3.00 May 15, 2007 Page 107 of 518
REJ09B0152-0300