HD64F38602R Datasheet, PDF (262/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc or 1tsubcyc will occur between clock halting and interrupt
acceptance.
7. When pins in port 1 are used for AEC input/output, the PFCR and PMR1 registers should be
set in the following order.
a. Set the PFCR register.
b. Set bits 4 to 0 after bit 5 (IRQAEC bit) in the PMR1 register has been cleared to 0.
c. Set bit 5 (IRQAEC bit) in the PMR1 register to 1. At this time, bits 4 to 0 should not be
changed and remain the same.
Rev. 3.00 May 15, 2007 Page 230 of 516
REJ09B0152-0300