HD64F38602R Datasheet, PDF (238/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Watchdog Timer
Initial
Bit
Bit Name Value R/W Description
2 to 0 
All 1

Reserved
These bits are always read as 1.
Notes: 1. Only 0 can be written to clear the flag.
2. Write operation is necessary because this bit controls data writing to other bit. This bit is
always read as 1.
3. Writing is possible only when the write conditions are satisfied.
12.2.3 Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD1 is set to 1. TCWD is initialized
to H'00.
Rev. 3.00 May 15, 2007 Page 206 of 516
REJ09B0152-0300