HD64F38602R Datasheet, PDF (484/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Appendix
5. Bit-Manipulation Instructions
Addressing Mode and
Instruction Length (bytes)
Mnemonic
Operation
BSET BSET #xx:3, Rd
B
2
BSET #xx:3, @ERd
B
4
BSET #xx:3, @aa:8
B
4
BSET Rn, Rd
B
2
BSET Rn, @ERd
B
4
BSET Rn, @aa:8
B
4
BCLR BCLR #xx:3, Rd
B
2
BCLR #xx:3, @ERd
B
4
BCLR #xx:3, @aa:8
B
4
BCLR Rn, Rd
B
2
BCLR Rn, @ERd
B
4
BCLR Rn, @aa:8
B
4
BNOT BNOT #xx:3, Rd
B
2
BNOT #xx:3, @ERd B
4
BNOT #xx:3, @aa:8 B
4
BNOT Rn, Rd
B
2
BNOT Rn, @ERd
B
4
BNOT Rn, @aa:8
B
4
BTST BTST #xx:3, Rd
B
2
BTST #xx:3, @ERd
B
4
BTST #xx:3, @aa:8
B
4
BTST Rn, Rd
B
2
BTST Rn, @ERd
B
4
BTST Rn, @aa:8
B
4
BLD BLD #xx:3, Rd
B
2
(#xx:3 of Rd8) ← 1
(#xx:3 of @ERd) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
(Rn8 of @ERd) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @ERd) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
(Rn8 of @ERd) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
¬ (#xx:3 of Rd8) → Z
¬ (#xx:3 of @ERd) → Z
¬ (#xx:3 of @aa:8) → Z
¬ (Rn8 of @Rd8) → Z
¬ (Rn8 of @ERd) → Z
¬ (Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
No. of
States*¹
Condition Code
I HNZVC
——————
2
——————
8
——————
8
——————
2
——————
8
——————
8
——————
2
——————
8
——————
8
——————
2
——————
8
——————
8
——————
2
——————
8
——————
8
——————
2
——————
8
——————
8
———
——
2
———
——
6
———
——
6
———
——
2
———
——
6
———
——
6
—————
2
Rev. 3.00 May 15, 2007 Page 452 of 516
REJ09B0152-0300