HD64F38602R Datasheet, PDF (74/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Source Origin
Reset pin/
watchdog timer

External interrupt
Trap instruction
TRAPA #0
Trap instruction
TRAPA #1
Trap instruction
TRAPA #2
Trap instruction
TRAPA #3

CPU

External interrupts

Comparators
RTC
Exception Sources
Reset
Reserved for system use
NMI
Trap instruction #0
Trap instruction #1
Trap instruction #2
Trap instruction #3
Reserved for system use
Direct transition by executing the
SLEEP instruction
Reserved for system use
IRQ0
IRQ1
IRQAEC
Reserved for system use
COMP0
COMP1
0.25-second overflow
0.5-second overflow
Second periodic overflow
Minute periodic overflow
Hour periodic overflow
Day-of-week periodic overflow
Week periodic overflow
Free-running overflow
Vector
Number
0
Vector Address
H'0000 to H'0001
Priority
High
1 to 6
7
8
H'0002 to H'000D
H'000E to H'000F
H'0010 to H'0011
9
H'0012 to H'0013
10
H'0014 to H'0015
11
H'0016 to H'0017
12
H'0018 to H'0019
13
H'001A to H'001B
14, 15
16
17
18
19, 20
21
22
23
24
25
26
27
28
29
30
H'001C to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
H'0026 to H'0029
H'002A to H'002B
H'002C to H'002D
H'002E to H'002F
H'0030 to H'0031
H'0032 to H'0033
H'0034 to H'0035
H'0036 to H'0037
H'0038 to H'0039
H'003A to H'003B
H'003C to H'003D Low
Rev. 3.00 May 15, 2007 Page 42 of 516
REJ09B0152-0300