HD64F38602R Datasheet, PDF (286/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
LSB
Serial Start
data bit
1 bit
Transmit/receive data
MSB
Parity
bit
Stop bit
5, 7, or 8 bits
1 bit,
or none
One unit of transfer data (character or frame)
1 or
2 bits
1
Mark state
Figure 14.2 Data Format in Asynchronous Communication
14.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the
SCK3 pin, the clock frequency should be 16 times the bit rate used (when the ABCS bit in SEMR
is 1, the clock frequency should be eight times the bit rate used). For details on selection of the
clock source, see table 14.10. When the SCI3 is operated on an internal clock, the clock can be
output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate,
and the phase is such that the rising edge of the clock is in the middle of the transfer data, as
shown in figure 14.3.
Clock
Serial data
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 3.00 May 15, 2007 Page 254 of 516
REJ09B0152-0300