HD64F38602R Datasheet, PDF (404/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 20 List of Registers
20.1 Register Addresses (Address Order)
The data bus width indicates the number of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Flash memory control register 1
Flash memory control register 2
Flash memory power control register
Erase block register 1
Flash memory enable register
RTC interrupt flag register
Second data register/free running
counter data register
Minute data register
Hour data register
Day-of-week data register
RTC control register 1
RTC control register 2
Clock source select register
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
Slave address register
I²C bus transmit data register
I²C bus receive data register
Abbre-
viation
FLMCR1
FLMCR2
FLPWCR
EBR1
FENR
RTCFLG
RSECDR
RMINDR
RHRDR
RWKDR
RTCCR1
RTCCR2
RTCCSR
ICCR1
ICCR2
ICMR
ICIER
ICSR
SAR
ICDRT
ICDRR
Address
H'F020
H'F021
H'F022
H'F023
H'F02B
H'F067
H'F068
H'F069
H'F06A
H'F06B
H'F06C
H'F06D
H'F06F
H'F078
H'F079
H'F07A
H'F07B
H'F07C
H'F07D
H'F07E
H'F07F
Module
Name
ROM
ROM
ROM
ROM
ROM
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
IIC2
IIC2
IIC2
IIC2
IIC2
IIC2
IIC2
IIC2
Data Bus Access
Width State
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
Rev. 3.00 May 15, 2007 Page 372 of 516
REJ09B0152-0300