HD64F38602R Datasheet, PDF (326/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.2 Relationship between Clock Polarity and Phase, and Data
Relationship between clock polarity and phase, and transfer data changes according to a
combination of the SSUMS bit in SSCRL and the CPOS and CPHS bits in SSMR. Figure 15.2
shows the relationship.
MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR.
When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is
started from MSB to LSB.
(1) When CPHS = 0, CPOS =0, and SSUMS = 0:
SSCK
SSO, SSI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 0 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
SCS
(3) When CPHS = 1 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
SCS
Figure 15.2 Relationship between Clock Polarity and Phase, and Data
Rev. 3.00 May 15, 2007 Page 294 of 516
REJ09B0152-0300