HD64F38602R Datasheet, PDF (253/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
Initial
Bit Bit Name Value R/W Description
2
CUEL
0
R/W Count-Up Enable L
Enables event clock input to ECL.
0: ECL event clock input is disabled (ECL value is
retained)
1: ECL event clock input is enabled
1
CRCH
0
R/W Counter Reset Control H
Controls resetting of ECH.
0: ECH is reset
1: ECH reset is cleared and count-up function is
enabled
0
CRCL
0
R/W Counter Reset Control L
Controls resetting of ECL.
0: ECL is reset
1: ECL reset is cleared and count-up function is
enabled
Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 221 of 516
REJ09B0152-0300