HD64F38602R Datasheet, PDF (136/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 ROM
6.2.5 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Initial
Bit
Bit Name Value R/W Description
7
FLSHE 0
R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
6 to 0 
All 0

Reserved
These bits are always read as 0.
6.3 On-Board Programming Modes
The available mode for programming/erasing of the flash memory is boot mode, which enables
on-board programming/erasure. On-board programming/erasure can also be performed in user
program mode. When this LSI starts after releasing the reset state, it enters a mode depending on
the signal levels on the TEST, NMI , and E7_0 pins, as shown in table 6.1. The input level of each
pin must be stable four states before the reset ends.
When entering the boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for initializing flash memory mounted on the user board or for a forcible
recovery if flash memory cannot be programmed or erased in user program mode. In user program
mode, individual blocks can be erased and programmed by branching to the user
programming/erasing control program prepared by the user.
Table 6.1 Setting Programming Modes
TEST
NMI
0
1
0
0
[Legend]
x: Don’t care.
E7_0
x
1
LSI State after Reset Released
User Mode
Boot Mode
Rev. 3.00 May 15, 2007 Page 104 of 516
REJ09B0152-0300