HD64F38602R Datasheet, PDF (107/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Clock Pulse Generators
(2) Wait Time
After the system clock is generated, the time required for the amplitude of the oscillation
waveform to increase, the oscillation frequency to stabilize, and the CPU and peripheral functions
to begin operating.
Oscillation waveform
(OSC2)
System clock (φ)
Oscillation
start time
Wait time
Operating mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Stabilization Wait Time
As the oscillation stabilization wait time required is the same as the oscillation stabilization time
(t_rc) at power-on, specified in the AC characteristics, set the STS2 to STS0 bits in SYSCR1 to
specify the time longer than the oscillation stabilization time (t_rc).
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an resonator connected to the system clock
oscillator, careful evaluation must be carried out on the mounting circuit before deciding the
oscillation stabilization wait time. For the wait time, secure the time required for the amplitude of
the oscillation waveform to increase and the oscillation frequency to stabilize. In addition, since
the oscillation start time differs according to mounting circuit constants, stray capacitance, and so
forth, suitable constants should be determined in consultation with the resonator manufacturer.
Rev. 3.00 May 15, 2007 Page 75 of 518
REJ09B0152-0300