HD64F38602R Datasheet, PDF (378/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
16.6 Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 16.21 shows the timing of the bit synchronous circuit and table 16.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
SCL
VIH
Internal SCL
Figure 16.21 Timing of Bit Synchronous Circuit
Table 16.4 Time for Monitoring SCL
CKS3
0
1
CKS2
0
1
0
1
Time for Monitoring SCL
7.5 tcyc
19.5 tcyc
17.5 tcyc
41.5 tcyc
Rev. 3.00 May 15, 2007 Page 346 of 516
REJ09B0152-0300