HD64F38602R Datasheet, PDF (21/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/38602R Group .............................................................. 2
Figure 1.2 Pin Assignment of H8/38602R Group (TNP-32) .......................................................... 3
Figure 1.3 Pin Assignment of H8/38602R Group (32P6U-A)........................................................ 3
Section 2 CPU
Figure 2.1 Memory Map................................................................................................................. 8
Figure 2.2 CPU Registers ............................................................................................................... 9
Figure 2.3 Usage of General Registers ......................................................................................... 10
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 11
Figure 2.5 General Register Data Formats (1).............................................................................. 13
Figure 2.5 General Register Data Formats (2).............................................................................. 14
Figure 2.6 Memory Data Formats................................................................................................. 15
Figure 2.7 Instruction Formats...................................................................................................... 26
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 32
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 33
Figure 2.11 CPU Operating States................................................................................................ 34
Figure 2.12 State Transitions ........................................................................................................ 35
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Same Address ............................................................................................................ 36
Section 3 Exception Handling
Figure 3.1 Reset Exception Handling Sequence........................................................................... 45
Figure 3.2 Block Diagram of Interrupt Controller........................................................................ 54
Figure 3.3 Flow up to Interrupt Acceptance ................................................................................. 55
Figure 3.4 Interrupt Exception Handling Sequence...................................................................... 56
Figure 3.5 Stack Status after Exception Handling ........................................................................ 57
Figure 3.6 Operation when Odd Address is Set in SP .................................................................. 58
Figure 3.7 PFCR and PMRB (or AEGSR) Setting and Interrupt Request
Flag Clearing Procedure .............................................................................................. 59
Section 4 Clock Pulse Generators
Figure 4.1 Block Diagram of Clock Pulse Generators.................................................................. 63
Figure 4.2 Typical Connection to Crystal Resonator.................................................................... 66
Figure 4.3 Typical Connection to Ceramic Resonator.................................................................. 66
Figure 4.4 Example of External Clock Input ................................................................................ 67
Figure 4.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 68
Figure 4.6 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator.................................. 69
Rev. 3.00 May 15, 2007 Page xxi of xxxii