HD64F38602R Datasheet, PDF (31/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10
Table 14.11
Table 14.12
Table 14.13
Table 14.14
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 1) (4)...................................................... 247
Relation between n and Clock .............................................................................. 248
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 248
BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) ................... 249
BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) ................... 250
Relation between n and Clock .............................................................................. 250
Data Transfer Formats (Asynchronous Mode)...................................................... 255
SMR Settings and Corresponding Data Transfer Formats.................................... 256
SMR and SCR Settings and Clock Source Selection............................................ 257
SSR Status Flags and Receive Data Handling...................................................... 262
IrCKS2 to IrCKS0 Bit Settings............................................................................. 273
SCI3 Interrupt Requests........................................................................................ 274
Transmit/Receive Interrupts ................................................................................. 275
Section 15 Synchronous Serial Communication Unit (SSU)
Table 15.1 Pin Configuration.................................................................................................. 284
Table 15.2 Relationship between Communication Modes and Input/Output Pins.................. 296
Table 15.3 Interrupt Requests ................................................................................................. 310
Section 16 I²C Bus Interface 2 (IIC2)
Table 16.1 Pin Configuration.................................................................................................. 313
Table 16.2 Transfer Rate ........................................................................................................ 316
Table 16.3 Interrupt Requests ................................................................................................. 345
Table 16.4 Time for Monitoring SCL..................................................................................... 346
Section 17 A/D Converter
Table 17.1 Pin Configuration.................................................................................................. 350
Table 17.2 Operating States of A/D Converter....................................................................... 354
Section 18 Comparators
Table 18.1 Pin Configuration.................................................................................................. 362
Table 18.2 Combination of CMR and CMLS Bits ................................................................. 364
Section 21 Electrical Characteristics
Table 21.1 Absolute Maximum Ratings ................................................................................. 385
Table 21.2 DC Characteristics ................................................................................................ 393
Table 21.3 Control Signal Timing .......................................................................................... 399
Table 21.4 Serial Interface Timing ......................................................................................... 402
Table 21.5 Synchronous Serial Communication Unit (SSU) Timing ..................................... 403
Table 21.6 I²C Bus Interface Timing ...................................................................................... 404
Table 21.7 A/D Converter Characteristics .............................................................................. 405
Table 21.8 Comparator Characteristics................................................................................... 407
Rev. 3.00 May 15, 2007 Page xxxi of xxxii