HD64F38602R Datasheet, PDF (190/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
10.3.2 Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer
output levels.
Initial
Bit Bit Name Value R/W Description
7
CCLR
0
R/W Counter Clear
The TCNT value is cleared by compare match A when
this bit is 1. When it is 0, TCNT operates as a free-
running counter.
6
CKS2
0
R/W Clock Select 2 to 0
5
CKS1
0
R/W Select the TCNT clock source.
4
CKS0
0
R/W 000: Internal clock: counts on φ
001: Internal clock: counts on φ/2
010: Internal clock: counts on φ/4
011: Internal clock: counts on φ/8
100: Internal clock: counts on φ
W
101: Internal clock: counts on φ /4
W
110: Internal clock: counts on φ_W/16
111: Counts on rising edges of the external event
(FTCI)
With a setting of 0xx, the timer W can be used only in
active mode or sleep mode. Do not make this setting in
subactive mode or subsleep mode.
When 100 is set in subactive mode or subsleep mode,
the timer W can be used only when φ is selected as
W
the CPU operating clock.
When 101 is set in subactive mode or subsleep mode,
the timer W can be used only when φ_W or φ_W/2 is
selected as the CPU operating clock.
3
TOD
0
R/W Timer Output Level Setting D
Sets the output value of the FTIOD pin until the first
compare match D is generated.
0: Output value is 0*
1: Output value is 1*
2
TOC
0
R/W Timer Output Level Setting C
Sets the output value of the FTIOC pin until the first
compare match C is generated.
0: Output value is 0*
1: Output value is 1*
Rev. 3.00 May 15, 2007 Page 158 of 516
REJ09B0152-0300