HD64F38602R Datasheet, PDF (89/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.7 Stack Status after Exception Handling
Figures 3.5 shows the stack after completion of interrupt exception handling.
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR^*
PCH
PCL
Even address
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
[Legend]
PCH: Upper 8 bits of program counter (PC)
PCL: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
After completion of interrupt
exception handling
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word length, starting from
an even-numbered address.
* Ignored when returning from the interrupt handling routine.
Figure 3.5 Stack Status after Exception Handling
3.7.1 Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.4 Interrupt Wait States
Item
Waiting time for completion of executing instruction*
Saving of PC and CCR to stack
Vector fetch
Instruction fetch
Internal processing
Note: * Excluding EEPMOV instruction.
States
1 to 23
4
2
4
4
Total
15 to 37
Rev. 3.00 May 15, 2007 Page 57 of 516
REJ09B0152-0300