HD64F38602R Datasheet, PDF (79/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.4.1 Interrupt Edge Select Register (IEGR)
IEGR selects whether interrupt requests of the NMI, ADTRG, IRQ1, and IRQ0 pins are generated
at the rising edge or falling edge.
Initial
Bit
Bit Name Value R/W Descriptions
7
NMIEG
0
R/W NMI Edge Select
0: Detects a falling edge of the NMI pin input
1: Detects a rising edge of the NMI pin input
6

0

Reserved
This bit is always read as 0.
5
ADTRGNEG 0
R/W ADTRG Edge Select
0: Detects a falling edge of the ADTRG pin input
1: Detects a rising edge of the ADTRG pin input
4 to 2 
All 0

Reserved
The write value should always be 0.
1
IEG1
0
R/W IRQ1 Edge Select
0: Detects a falling edge of the IRQ1 pin input
1: Detects a rising edge of the IRQ1 pin input
0
IEG0
0
R/W IRQ0 Edge Select
0: Detects a falling edge of the IRQ0 pin input
1: Detects a rising edge of the IRQ0 pin input
Rev. 3.00 May 15, 2007 Page 47 of 516
REJ09B0152-0300