HD64F38602R Datasheet, PDF (75/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
Source Origin
Exception Sources
WDT
WDT overflow (interval timer)
Asynchronous
event counter
Asynchronous event counter
overflow
Timer B1
Overflow
Synchronous serial Overrun error (SSU)
communication unit Transmit data empty (SSU)
(SSU)/
Transmit end (SSU)
Receive data full (SSU)
Conflict error (SSU)/
Vector
Number
31
32
Vector Address
H'003E to H'003F
H'0040 to H'0041
Priority
High
33
H'0042 to H'0043
34
H'0044 to H'0045
IIC2*
Transmit data empty (IIC2)
Transmit end (IIC2)
Receive data full (IIC2)
NACK detection (IIC2)
Arbitration (IIC2)
Overrun error (IIC2)
Timer W
Input capture A/compare match A 35
H'0046 to H'0047
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Overflow

Reserved for system use
36
H'0048 to H'0049
SCI3
Transmit end
37
H'004A to H'004B
Transmit data empty
Receive data full
Overrun error
Framing error
Parity error
A/D converter
A/D conversion end
38
H'004C to H'004D

Reserved for system use
39
H'004E to H'004F Low
Note: * The SSU and IIC share the same vector address. When using the IIC, shift the SSU to
standby mode using CKSTPR2.
Rev. 3.00 May 15, 2007 Page 43 of 516
REJ09B0152-0300