HD64F38602R Datasheet, PDF (280/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.4 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw*
0
1
2
φ/16
1
0
3
φ/64
1
1
Note: * In subactive or subsleep mode, the SCI3 can be operated only when the CPU operating
clock is φ .
W
Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s)
φ (MHz)
ABCS = 0
ABCS = 1
n
0.0328*
1025
2050
0
0.0384*
1200
2400
0
2
62500
125000
0
2.097152
65536
131072
0
2.4576
76800
153600
0
3
93750
187500
0
3.6864
115200
230400
0
4
125000
250000
0
4.194304
131072
262144
0
4.9152
153600
307200
0
5
156250
312500
0
6
187500
375000
0
6.144
192000
384000
0
7.3728
230400
460800
0
8
250000
500000
0
9.8304
307200
614400
0
10
312500
625000
0
Note: * When CKS1 = 0 and CKS0 = 1 in SMR
Setting
N
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 3.00 May 15, 2007 Page 248 of 516
REJ09B0152-0300