HD64F38602R Datasheet, PDF (147/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 ROM
The FLMCR1, FLMCR2, and EBR1 settings are retained, however programming mode or erasing
mode is aborted when the error occurred. Programming mode or erasing mode cannot be re-
entered by re-setting the P or E bit. However, settings of the PV and EV bits are retained, and a
transition can be made to the verifying mode. The error protection state can be cleared only by a
reset.
6.6 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from the
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
Table 6.7 Flash Memory Operating States
LSI Operating State
Active mode
Subactive mode
Sleep mode
Subsleep mode
Watch mode
Standby mode
Flash Memory Operating State
PDWND = 0 (Initial Value)
PDWND = 1
Normal operating mode
Normal operating mode
Power-down mode
Normal operating mode
Normal operating mode
Normal operating mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Rev. 3.00 May 15, 2007 Page 115 of 518
REJ09B0152-0300