HD64F38602R Datasheet, PDF (17/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU) ............................283
15.1 Features.............................................................................................................................. 283
15.2 Input/Output Pins ............................................................................................................... 284
15.3 Register Descriptions ......................................................................................................... 285
15.3.1 SS Control Register H (SSCRH) .......................................................................... 285
15.3.2 SS Control Register L (SSCRL) ........................................................................... 287
15.3.3 SS Mode Register (SSMR) ................................................................................... 289
15.3.4 SS Enable Register (SSER) .................................................................................. 290
15.3.5 SS Status Register (SSSR) .................................................................................... 291
15.3.6 SS Receive Data Register (SSRDR) ..................................................................... 293
15.3.7 SS Transmit Data Register (SSTDR).................................................................... 293
15.3.8 SS Shift Register (SSTRSR)................................................................................. 293
15.4 Operation ........................................................................................................................... 293
15.4.1 Transfer Clock ...................................................................................................... 293
15.4.2 Relationship between Clock Polarity and Phase, and Data................................... 294
15.4.3 Relationship between Data Input/Output and Shift Register ................................ 295
15.4.4 Communication Modes and Pin Functions ........................................................... 296
15.4.5 Operation in Clocked Synchronous Communication Mode.................................. 297
15.4.6 Operation in Four-Line Bus Communication Mode ............................................. 303
15.4.7 Initialization in Four-Line Bus Communication Mode......................................... 304
15.4.8 Serial Data Transmission ...................................................................................... 305
15.4.9 Serial Data Reception ........................................................................................... 307
15.4.10 SCS Pin Control and Arbitration .......................................................................... 309
15.4.11 Interrupt Requests ................................................................................................. 310
15.5 Usage Note......................................................................................................................... 310
Section 16 I²C Bus Interface 2 (IIC2) ................................................................311
16.1 Features.............................................................................................................................. 311
16.2 Input/Output Pins ............................................................................................................... 313
16.3 Register Descriptions ......................................................................................................... 314
16.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 314
16.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 317
16.3.3 I²C Bus Mode Register (ICMR)............................................................................ 319
16.3.4 I²C Bus Interrupt Enable Register (ICIER) ........................................................... 321
16.3.5 I²C Bus Status Register (ICSR)............................................................................. 323
16.3.6 Slave Address Register (SAR).............................................................................. 326
16.3.7 I²C Bus Transmit Data Register (ICDRT)............................................................. 326
16.3.8 I²C Bus Receive Data Register (ICDRR).............................................................. 327
16.3.9 I²C Bus Shift Register (ICDRS)............................................................................ 327
Rev. 3.00 May 15, 2007 Page xvii of xxxii